Receiving circuit

ABSTRACT

A receiving circuit includes a positive-side level judgment circuit, a negative-side level judgment circuit, and a gate circuit, and is configured to receive input of an AMI-coded signal, convert the signal to a binary output signal, and output the same. The positive-side level judgment circuit judges whether the voltage of an input signal is greater or less than a threshold on the positive side. The threshold on the positive side is provided with a hysteresis characteristic by a positive feedback. The negative-side level judgment circuit judges whether the voltage of an input signal is greater or less than a threshold on the negative side. The threshold on the negative side is provided with a hysteresis characteristic by a positive feedback loop. The gate circuit logically combines the outputs of the positive-side and negative-side level judgment circuits so as to generate the output signal.

TECHNICAL FIELD

The present invention relates to a receiving circuit. More specifically,the present invention relates to a receiving circuit for receiving anAMI coded signal in a transmission device in the case where atransmission path is long or has many branches such as for transmissionbetween an outdoor unit and an indoor unit of an air conditioner.

BACKGROUND ART

A signal encoded to an alternate mark inversion (AMI) code signal(hereinafter referred to as “AMI signal”) is a type of transmissionsignal used for transmission of digital signals. An AMI signal is usedin a home bus system (HBS) and the like. An output AMI signal has threevoltage levels: zero, positive, and negative, and the AMI signal flowsthrough a positive signal line and a negative signal line. In acommunication system using this signal, a logic “1” signal is set to thezero level; whereas a logic “0” signal is alternately set to positiveand negative levels.

As disclosed in Patent Document 1, there is an air conditioner in whichthe exchange of data between an outdoor unit and an indoor unit isachieved by transmission of an AMI signal. Here, for example, theoutdoor unit is equipped with a controller including a protocolcontroller, a transmitting circuit, a receiving circuit, and the like,and the transmitting circuit and the receiving circuit are connected toa positive signal line and a negative signal line that are extended tothe indoor unit and the like. The receiving circuit receives an AMIsignal from the positive signal line and the negative signal line;converts a positive pulse and a negative pulse of the signal to a lowpulse (logic “0”), converts the zero level of the signal to a high pulse(logic “1”); and transmits the digital output to the protocolcontroller.

FIG. 9 shows an example of a receiving circuit used in a current airconditioner. This receiving circuit includes: coupling condensers C1,C2; an attenuator including resistors R4, R5, R7, and R8; a differentialamplification circuit constituted by transistors Q1 and Q2 and constantcurrent sources I1 and I2; resistors R1 and R2 for receiving a currentoutput from the transistors Q1 and Q2 and converting it to a voltage;comparators U1 and U2 configured to judge an input signal by comparingeach voltage output from the resistors R1 and R2 with a referencevoltage V3; a gate circuit U3 configured to invert a logical sum of eachoutput of the comparators U1 and U2; and the like. In FIG. 9, a symbolVCC5 represents a supply voltage. The receiving circuit receives an AMIsignal from a positive signal line 91 and a negative signal line 92, andtransmits a binary output signal from the gate circuit U3 to theprotocol controller (not shown). In addition, in the receiving circuitshown in FIG. 9, a portion surrounded by dotted lines is embedded in anintegrated circuit 59.

<Patent Document 1>

Japanese Patent Application Publication No. 8-195761

DISCLOSURE OF THE INVENTION Object to be Achieved by the PresentInvention

In the communication system of an air conditioner which uses an AMIsignal, a transmission path between an outdoor unit installed on theroof of a building or the like and an indoor unit installed in theceiling of each room tends to be long. In this case, it is not only thatthe waveform of the signal may become distorted while the signal passesthrough the transmission path; but it is also that the effects of noiseand reflected waves are exerted on the waveform, causing a pulseoriginally generated as one pulse to be divided into a plurality ofpulses when the signal is converted by the receiving circuit. Inaddition, also in the case where the transmission path has manybranches, a similar problem as described above may occur.

As shown in FIG. 10, the waveform (receive waveform) of the signal atthe time of input to the receiving circuit is distorted with respect tothe transmit waveform and the effects of noise and reflected waves aresuperimposed. The receiving circuit that received a signal having suchwaveform converts the signal to a logic “0” digital signal and a logic“1” digital signal using a threshold voltage Vth+ on the positive sideand a threshold voltage Vth− on the negative side as thresholds.Specifically, a signal in the range from the level Vth+ to the levelVth− is converted to a logic “1” level and a signal beyond the levelVth+ and below the level Vth− is converted to a logic “0” level.Therefore, in the case of the receive waveform as shown in the middleportion of FIG. 10, a pulse originally generated as one pulse is dividedinto and identified as a plurality of pulses due to the effects of noiseand reflected waves as shown in the lower portion of FIG. 10. As aresult, there is a case where the protocol controller that received thedigital output signal from the receiving circuit judges that data haserror, which may consequently cause communication error.

In addition, in the conventional receiving circuit shown in FIG. 9, theresistors R4 and R5 that are electronic components to determine theinput sensitivity together with the resistors R7 and R8 are embedded inthe integrated circuit 59. This contributes to a reduction of the numberof external electronic components to the integrated circuit 59. However,recent technical investigations by the inventor of the presentapplication are revealing that the effects of noise and reflected wavesmay be the factors that reduce the accuracy of data conversion in thereceiving circuit.

An object of the present invention is to provide a receiving circuitcapable of reducing the frequency of occurrence of communication error.

Means to Achieve the Object

A receiving circuit according to a first aspect of the present inventionis a receiving circuit that receives input of an AMI signal, convertsthe signal to a binary output signal, and outputs the same, thereceiving circuit including a first judging means, a second judgingmeans, an output signal generating means, a first hysteresis generatingmeans, and a second hysteresis generating means. The first judging meansjudges whether an input signal is greater or less than a first thresholdon the positive side. The second judging means judges whether an inputsignal is greater or less than a second threshold on the negative side.The output signal generating means generates the output signal based onjudgment results of the first judging means and the second judgingmeans. The first hysteresis generating means provides a hysteresischaracteristic to the first threshold. The second hysteresis generatingmeans provides a hysteresis characteristic to the second threshold.

In the conventional receiving circuit as shown in FIG. 9, each of thethreshold on the positive side and the threshold on the negative side isfixed as one numerical value. Thus, when an AMI signal affected by noiseand reflected waves is received, a pulse originally generated as onepulse as shown in the lower portion of FIG. 10 is likely to be presentedas a plurality of pulses in the output signal.

In contrast to the above, in the receiving circuit of the first aspectof the present invention, each of the first threshold on the positiveside and the second threshold on the negative side is provided with ahysteresis characteristic. Consequently, the response of each judgingmeans to a disturbed portion of the AMI signal affected by noise andreflected waves becomes less sensitive, which reduces the occurrence ofthe problem that an original pulse is divided into a plurality of pulsesin the output signal due to noise and the like. In this way, thereceiving circuit according to the first aspect of the present inventioncan reduce the frequency of occurrence of communication error, comparedwith the conventional receiving circuit.

A receiving circuit according to a second aspect of the presentinvention is the receiving circuit according to the first aspect of thepresent invention, wherein the first hysteresis generating means setsthe first threshold to a first threshold for increase on the positiveside and a first threshold for decrease on the positive side byproviding a hysteresis characteristic. The first judging means invertsthe result of judgment between the two levels when the voltage of theinput signal exceeds the first threshold for increase on the positiveside during the increase of the voltage of the input signal. Further,the first judging means inverts the result of judgment between the twolevels when the voltage of the input signal lowers the first thresholdfor decrease on the positive side during the decrease of the voltage ofthe input signal. In addition, the second hysteresis generating meanssets the second threshold to a second threshold for increase on thenegative side and a second threshold for decrease on the negative sideby providing a hysteresis characteristic. The second judging meansinverts the result of judgment between the two levels when the voltageof the input signal exceeds the second threshold for increase on thenegative side during the increase of the voltage of the input signal.Further, the second judging means inverts the result of judgment betweenthe two levels when the voltage of the input signal lowers the secondthreshold for decrease on the negative side during the decrease of thevoltage of the input signal.

Here, the hysteresis characteristics for reducing the effects ofdisturbance of the waveform due to the noise and reflected waves forjudging the voltage of the input signal are provided at two points (thefirst threshold and the second threshold), thereby reducing thefrequency of occurrence of communication error.

A receiving circuit according to a third aspect of the present inventionis a receiving circuit that receives input of an AMI coded differentialsignal, converts the signal to a binary output signal, and outputs thesame, the receiving circuit including a differential amplifying means, afirst judging means, a second judging means, an output signal generatingmeans, a first hysteresis generating means, and a second hysteresisgenerating means. The differential amplifying means converts thedifferential signal to a normal signal. Each of the first judging meansand the second judging means judges whether the normal signal is greateror less than a threshold. The output signal generating means generatesthe output signal based on judgment results of the first judging meansand the second judging means. The first hysteresis generating meansprovides a hysteresis characteristic to a threshold of the first judgingmeans. The second hysteresis generating means provides a hysteresischaracteristic to a threshold of the second judging means.

In the conventional receiving circuit as shown in FIG. 9, the thresholdis fixed as one numerical value. Thus, when an AMI signal affected bynoise and reflected waves is received, a pulse originally generated asone pulse as shown in the lower portion of FIG. 10 is likely to bepresented as a plurality of pulses in the output signal.

In contrast to the above, in the receiving circuit of the third aspectof the present invention, a hysteresis characteristic is provided to thethreshold in each of the first judging means and the second judgingmeans. Consequently, the response of each judging means to a disturbedportion of the AMI signal affected by noise and reflected waves becomesless sensitive, which reduces the occurrence of the problem that anoriginal pulse is divided into a plurality of pulses in the outputsignal due to noise and the like. In this way, the receiving circuitaccording to the third aspect of the present invention can reduce thefrequency of occurrence of communication error, compared with theconventional receiving circuit.

A receiving circuit according to a fourth aspect of the presentinvention is a receiving circuit that receives input of an AMI-codedsignal, converts the signal to a binary output signal, and outputs thesame, the receiving circuit including an attenuator and a conversionunit. The attenuator includes a plurality of electronic components, andis configured to attenuate an input signal. The conversion unit convertsan input signal attenuated by the attenuator to the output signal. Inaddition, the conversion unit is embedded in an integrated circuit.Further, the electronic components of the attenuator are arrangedoutside the integrated circuit.

In the conventional receiving circuit shown in FIG. 9, because of anattenuator 60 including the resistors R4, R5, R7, and R8, the voltageattenuation ratio of the input signal is determined as follows, providedthat the resistance of the resistor R4 is the same as the resistance ofthe resistor R5 and the resistance of the resistor R7 is the same as theresistance of the resistor R8:

(resistance of resistor R4)/(resistance of resistor R4+resistance ofresistor R7).

However, in the conventional receiving circuit shown in FIG. 9, theresistors R4 and R5, which are electronic components that determine theinput sensitivity together with resistors R7 and R8, are embedded in theintegrated circuit 59. Typically, while an ion implantation resistor, apolysilicon resistor, and the like are used inside the integratedcircuit, a metal film resistor and a carbon film resistor are used asexternal resistors. The degree of the change in the resistance due tothe ambient temperature is different between the resistors R4 and R5 inthe integrated circuit 59 and the external resistors R7 and R8.Generally, a resistor in the integrated circuit has poor temperaturecharacteristics, and an external resistor has good temperaturecharacteristics. If the resistors R4, R5, R7, R8 had the sametemperature characteristics, the attenuation ratio of the input signalwould be maintained constant even when the ambient temperature varied.However, it is not the case, and the temperature characteristics of theresistors R4 and R5 in the integrated circuit are different from thetemperature characteristics of the external resistors R7 and R8. Thus,the attenuation rate is affected by the temperature.

Accordingly, in the conventional receiving circuit, the input signalattenuation rate of the attenuator is affected by the temperature, whichincreases the sensitivity of the signal and in turn susceptibilitythereof to the noise or reduces the sensitivity of the signal and inturn susceptibility thereof to a reflected wave in the negativedirection.

In contrast to the above, because the receiving circuit according to thefourth aspect of the present invention has a configuration in which theelectronic components such as the resistors and the like constitutingthe attenuator are arranged outside the integrated circuit, it ispossible to maintain the attenuation rate substantially constant evenwhen the ambient temperature varies. Thus, in the receiving circuit ofthe fourth aspect of the present invention, the frequency of occurrenceof communication error is reduced.

A receiving circuit according to a fifth aspect of the present inventionis the receiving circuit of the fourth aspect of the present invention,wherein the conversion unit has a differential amplifying meansconfigured to convert the input signal from a differential signal to anormal signal, and an output signal generating means configured toconvert the normal signal to the output signal.

A receiving circuit according to a sixth aspect of the present inventionis the receiving circuit of the fourth or fifth aspect of the presentinvention, wherein a power supply connected to the electronic componentsof the attenuator is pulled out from inside to outside the integratedcircuit.

A receiving circuit according to a seventh aspect of the presentinvention is the receiving circuit of the fourth or fifth aspect of thepresent invention, wherein a power supply connected to the electroniccomponents of the attenuator is generated inside or outside theintegrated circuit.

EFFECTS OF THE PRESENT INVENTION

The receiving circuit according to the first and second aspects of thepresent invention reduces the sensitivity of the response of eachjudging means to a disturbed portion of the AMI signal affected by noiseand reflected waves, which consequently reduces the occurrence of theproblem that an original pulse is divided into a plurality of pulses inthe output signal due to noise and the like and reduces the frequency ofoccurrence of communication error, compared with the conventionalreceiving circuit.

The receiving circuit according to the third aspect of the presentinvention reduces the sensitivity of the response of each judging meansto a disturbed portion of the AMI signal affected by noise and reflectedwaves, which consequently reduces the occurrence of the problem that anoriginal pulse is divided into a plurality of pulses in the outputsignal due to noise and the like and reduces the frequency of occurrenceof communication error, compared with the conventional receivingcircuit.

In the receiving circuit according to the fourth through seventh aspectsof the present invention, it is possible to maintain the attenuationrate of the attenuator substantially constant even when the ambienttemperature vanes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic configuration diagram of an air conditioner inwhich a receiving circuit according to the present invention isemployed.

FIG. 2 is a view showing a configuration of a receiving circuit in afirst embodiment.

FIG. 3 is a schematic diagram showing hysteresis characteristics forthreshold voltages on the positive and negative sides.

FIG. 4 is a view showing an example of an input signal and a differencein output signals due to hysteresis characteristics.

FIG. 5 is a view showing a configuration of a receiving circuit in asecond embodiment.

FIG. 6 is a view showing a configuration of a receiving circuit in athird embodiment.

FIG. 7 is a view showing a configuration of a receiving circuit in afourth embodiment.

FIG. 8 is a block diagram of the receiving circuit in the fourthembodiment.

FIG. 9 is a view showing a configuration of a conventional receivingcircuit.

FIG. 10 is a view showing a problem in an output signal in theconventional receiving circuit.

DESCRIPTION OF THE REFERENCE SYMBOLS

-   10 Receiving circuit-   31 Positive-side level judgment circuit-   32 Negative-side level judgment circuit-   41, 42 Positive feedback-   51, 52,53 Integrated circuit-   61, 62, 63 Attenuator-   R4, R5, R7, R8, R15, R16 Resistor constituting attenuator-   U1, U2 Comparator

BEST MODE FOR CARRYING OUT THE INVENTION Air Conditioner

FIG. 1 shows a schematic configuration of an air conditioner in which atransmission device including a receiving circuit according to thepresent invention is used. An air conditioner 1 is installed in abuilding such as a building and includes one or a plurality ofrefrigeration systems. In each refrigeration system, a closedrefrigerant circuit is formed by one or a plurality of outdoor units 2and a plurality of indoor units 3 connected to the outdoor units 2. Inaddition, in each refrigeration system, the outdoor units 2 and theindoor units 3 are connected by a communication line 5. When a centralcontroller 4 is present as shown in FIG. 1, the central controller 4 isalso connected by the communication line 5. The communication line 5 isprovided to transmit air conditioning control data and air conditioningmonitoring data, and includes a positive signal line 91 and a negativesignal line 92 (see FIG. 2 and the like).

This air conditioner 1 employs a transmission system to transmit an AMIsignal over the communication line 5. In this system, a signal isgenerated by a method in which a logic “1” signal is set to the zerolevel; whereas a logic “0” signal is alternately set to positive andnegative levels at the time of transmission. In other words, an AMIsignal has three voltage levels: zero, positive, and negative (see theupper portion of FIG. 10).

Each of the outdoor units 2, the indoor units 3, and the like connectedto the communication line 5 has a transmission device equipped with atransmitting circuit, a receiving circuit, a protocol controller, andthe like. The receiving circuit among these devices is described indetail below.

First Embodiment Configuration of the Receiving Circuit

FIG. 2 shows a receiving circuit according to a first embodiment of thepresent invention. A receiving circuit 10 includes coupling condensersC1 and C2, an attenuator 60, a differential amplification circuit 30, apositive-side level judgment circuit 31, a negative-side level judgmentcircuit 32, a gate circuit U3, and the like.

The coupling condensers C1 and C2 block DC voltage superimposed on thecommunication line 5 (the positive signal line 91 and the negativesignal line 92). The attenuator 60 includes resistors R4, R5, R7, andR8, and lowers the level of an input signal. The differentialamplification circuit 30 includes transistors Q1 and Q2 and constantcurrent sources I1 and I2, and converts an input signal that is adifferential signal to a normal signal. The resistors R1 and R2 receivecurrent output from the collectors of the transistors Q1 and Q2 andconvert the current to voltage.

The positive-side level judgment circuit 31 includes a comparator U1,and a resistor R13 for providing a hysteresis characteristic by adding apositive feedback 41 to the comparator U1. The comparator U1 judges thepositive polarity of an input signal by comparing the voltage outputfrom the resistor R2 with a reference voltage V3.

This comparator U1 is a comparator with hysteresis because of thepositive feedback 41 including the resistor R13 inserted between thepositive input and the output of the comparator. When the input signalis 0V, an output of the comparator U1 is L (low), which thus means thatthe resistor R2 is connected to the ground through the resistor R13 inthe positive feedback. Here, a combined resistance R0 of the resistanceof the resistor R2 and the resistance of the resistor R13 is determinedby the following equation:

$\begin{matrix}{{R\; 0} = {\frac{R\; 2 \times R\; 13}{{R\; 2} + {R\; 13}}.}} & {< {{Equation}\mspace{14mu} 1} >}\end{matrix}$

A voltage VQ2C of the collector of the transistor Q2 is determined bythe following equation:

$\begin{matrix}{{{VQ}\; 2C} = {{{VCC}\; 5 \times \frac{R\; 13}{{R\; 2} + {R\; 13}}} - {{Ic} \times R\; 0.}}} & {< {{Equation}\mspace{14mu} 2} >}\end{matrix}$

The symbol Ic represents a collector current of the transistor Q2. Next,when the voltage of the input signal rises, the collector current Ic ofthe transistor Q2 is attenuated, and the reduced amount of current flowsto the transistor Q1 side. Accordingly, the Ic in the above equation isreduced, and the VQ2C is increased beyond the reference voltage V3.Then, the output of the comparator U1 is inverted, changing from L (low)to H (high). Then, one end of the resistor R13 connected to the outputof the comparator U1 reaches a level of a supply voltage VCC5, and atthis instance, a collector voltage VQ2C of the transistor Q2 changesaccording to the following equation:

VQ2C=VCC5−Ic×R0  <Equation 3>

The amount of voltage ΔVQ2C that changes at this instance is thedifference between the above two expressions, and is determined by thefollowing equation:

$\begin{matrix}{{\Delta \; {VQ}\; 2C} = {{VCC}\; 5{\left( \frac{R\; 2}{{R\; 2} + {R\; 13}} \right).}}} & {< {{Equation}\mspace{14mu} 4} >}\end{matrix}$

This amount of voltage ΔVQ2C provides a hysteresis characteristic.Provided that a gain by the differential amplification circuit 30 is A,hysteresis Vh is determined by the following equation:

$\begin{matrix}{{Vh} = {A \times {VCC}\; 5{\left( \frac{R\; 2}{{R\; 2} + {R\; 13}} \right).}}} & {< {{Equation}\mspace{14mu} 5} >}\end{matrix}$

The negative-side level judgment circuit 32 includes a comparator U2,and a resistor R14 for providing a hysteresis characteristic by adding apositive feedback 42 to the comparator U2. The comparator U2 judges thenegative polarity of an input signal by comparing the voltage outputfrom the resistor R1 with the reference voltage V3.

This comparator U2 is a comparator with hysteresis because of thepositive feedback 42 including the resistor R14 inserted between thepositive input and output of the comparator. The principle of provisionof a hysteresis characteristic by the positive feedback 42 is the sameas provision of a hysteresis characteristic by the above describedpositive feedback 41, so that the description thereof is omitted.

The gate circuit U3 is a NOR gate that inverts a logical sum of outputsof the comparators U1 and U2, and is configured to output a logic “0” orlogic “1” output signal.

<Characteristics of the Receiving Circuit>

In the conventional receiving circuit as shown in FIG. 9, each of thethreshold voltage Vth+ on the positive side and the threshold voltageVth− on the negative side (see the middle portion of FIG. 10) is fixedas one numerical value. Thus, when an AMI signal affected by noise andreflected waves is received, a pulse originally generated as one pulseas shown in the lower portion of FIG. 10 is relatively likely to bepresented as a plurality of pulses in the output signal.

In contrast to the above, in the receiving circuit 10 of the firstembodiment shown in FIG. 2, the comparators U1 and U2 are comparatorswith hysteresis. Thus, each of the threshold voltage on the positiveside and the threshold voltage on the negative side is provided with ahysteresis characteristic. Specifically, as shown in FIG. 3, withrespect to the voltage of an AMI signal input from the positive signalline 91 and the negative signal line 92 (hereinafter referred to as“input voltage”), the threshold on the positive side is divided into twothresholds V1off and V1on, and the threshold on the negative side isdivided into two threshold V2off and V2on. In the case where the inputvoltage is positive, when the input voltage is increasing, the outputvoltage is inverted (changed from a high voltage Voh to a low voltageVol) when the input voltage exceeds the threshold V1on: whereas when theinput voltage is decreasing, the output voltage is inverted (changedfrom the low voltage Vol to the high voltage Voh) when the input voltagelowers the threshold V1off. On the other hand, in the case where theinput voltage is negative, when the input voltage is increasing, theoutput voltage is inverted (changed from the low voltage Vol to the highvoltage Voh) when the input voltage exceeds the threshold V2off: whereaswhen the input voltage is decreasing, the output voltage is inverted(changed from the high voltage Voh to the low voltage Vol) when theinput voltage lowers the threshold V2on.

Accordingly, in the case of the receiving circuit 10 according to thefirst embodiment, even when an AMI signal is affected by noise andreflected waves during transmission and consequently the receivewaveform of an input signal is disturbed as shown in the upper portionof FIG. 4, the occurrence of the problem that a pulse is divided into aplurality of pulses in the output signal due to the effects of noise andreflected waves is reduced (see the output signal on the lower portionof FIG. 4). By contrast, when the conventional receiving circuit inwhich a hysteresis characteristic is not provided from outside is used,as shown in the middle portion of FIG. 4, due to the effects ofreflected waves for example, a pulse that was not originally present ismistakenly identified, generating additional pulses in the outputsignal.

In this way, in the receiving circuit 10, the frequency of occurrence ofcommunication error is reduced, compared with the conventional receivingcircuit as shown in FIG. 9.

Second Embodiment Configuration of the Receiving Circuit

FIG. 5 shows a receiving circuit according to a second embodiment of thepresent invention. This receiving circuit includes the couplingcondensers C1 and C2, an attenuator 61, the differential amplificationcircuit 30, the comparators U1 and U2, the gate circuit U3, and thelike.

The coupling condensers C1 and C2 block DC voltage superimposed on thecommunication line 5 (the positive signal line 91 and the negativesignal line 92). The attenuator 61 includes the resistors R4, R5, R7,and R8, and lowers the level of an input signal. The differentialamplification circuit 30 includes the transistors Q1 and Q2 and theconstant current sources I1 and I2. The resistors R1 and R2 receivecurrent output from the collectors of the transistors Q1 and Q2 andconvert the current to voltage. The comparator U1 judges the positivepolarity of an input signal by comparing the voltage output from theresistor R2 with the reference voltage V3. The comparator U2 judges thenegative polarity of an input signal by comparing the voltage outputfrom the resistor R1 with the reference voltage V3. The gate circuit U3is a NOR gate that inverts a logical sum of outputs of the comparatorsU1 and U2, and is configured to output a logic “0” or logic “1” outputsignal.

The receiving circuit according to the second embodiment has aconfiguration in which all of the resistors R4, R5, R7, and R8constituting the attenuator 61 are external resistors arranged outsidethe integrated circuit 51, whereas the conversion unit (such as thedifferential amplification circuit 30, the comparators U1 and U2, thegate circuit U3, and the like) that converts an input signal whose levelis reduced by the attenuator 61 to an output signal is embedded in theintegrated circuit 51.

<Characteristics of the Receiving Circuit>

In the conventional receiving circuit shown in FIG. 9, because of theattenuator 60 including the resistors R4, R5, R7, and R8, the voltageattenuation ratio of the input signal is determined as follows, providedthat the resistance of the resistor R4 is the same as the resistance ofthe resistor R5 and the resistance of the resistor R7 is the same as theresistance of the resistor R8:

(resistance of resistor R4)/(resistance of resistor R4+resistance ofresistor R7).

Therefore, an input sensitivity Vth of the entire receiving circuit isdetermined by the following equation, provided that the inputsensitivity of the integrated circuit 59 is Vs:

$\begin{matrix}{{Vth} = {{Vs} \times {\frac{{R\; 4} + {R\; 7}}{R\; 4}.}}} & {< {{Equation}\mspace{14mu} 6} >}\end{matrix}$

Among these, the resistors R4 and R5 are polysilicon resistors and/orion implantation resistors having poor temperature characteristicsformed in the integrated circuit 59, whereas the resistors R7 and R8 areexternal resistors having good temperature characteristics. In this way,in the conventional receiving circuit shown in FIG. 9, the degree of thechange in the resistance due to the ambient temperature is differentbetween the resistors R4 and R5 in the integrated circuit 59 and theexternal resistors R7 and R8.

Therefore, if the resistors R4, R5, R7, R8 had the same temperaturecharacteristics, the attenuation ratio of the input signal would bemaintained constant even when the ambient temperature varied. However,the temperature characteristics of the resistors R4 and R5 in theintegrated circuit 59 are different from the temperature characteristicsof the external resistors R7 and R8, so that the attenuation rate isaffected by the temperature and the threshold levels vary. In this way,when the threshold levels vary, the communication quality is degraded.

In contrast to the above, the receiving circuit according to the secondembodiment in FIG. 5 has a configuration in which all of the resistorsR4, R5, R7, and R8 constituting the attenuator 61 are arranged outsidethe integrated circuit 51, and thus it is possible to maintain theattenuation rate substantially constant even when the ambienttemperature varies. Thus, the threshold levels (absolute values of thethreshold voltages Vth+ and Vth− in FIG. 10) are stably maintained.Therefore, in this receiving circuit, the communication quality isimproved compared to the conventional receiving circuit.

Third Embodiment

FIG. 6 shows a receiving circuit according to a third embodiment of thepresent invention. This receiving circuit has basically the sameconfiguration as the receiving circuit according to the above secondembodiment except for an attenuator 62, so that only different part ofthe configuration is described.

In the receiving circuit according to the above second embodiment, thevoltage of a voltage source V2 in the integrated circuit 51 is led outfrom the integrated circuit 51, and the resistors R4 and R5 areconnected thereto: whereas in the receiving circuit according to thethird embodiment, a voltage source V2 a is generated outside theintegrated circuit 52, thus reducing the number of pins extending out ofthe integrated circuit 52.

The configuration of the voltage source V2 a outside the integratedcircuit 52 in the receiving circuit of the third embodiment is notparticularly limited, however, as shown in FIG. 6, for example, it maybe simply configured such that the supply voltage VCC 5 is divided byresistors. In this case, the resistances of the external resistors R4,R5, R15, and R16 of the integrated circuit 52 are determined to satisfythe following two equations:

$\begin{matrix}{{V\; 2a} = {{VCC}\; 5 \times {\frac{R\; 16}{{R\; 15} + {R\; 16}}.}}} & {< {{Equation}\mspace{14mu} 7} >} \\{{{R\; 4} = {R5}}\operatorname{>>}{\frac{R\; 15 \times R\; 16}{{R\; 15} + {R\; 16}}.}} & {< {{Equation}\mspace{14mu} 8} >}\end{matrix}$

Fourth Embodiment

FIGS. 7 and 8 show a receiving circuit according to a fourth embodimentof the present invention. FIG. 8 shows a block diagram of the receivingcircuit.

This receiving circuit is a combination of the receiving circuitaccording to the above first embodiment and the receiving circuitaccording to the above third embodiment, and includes the couplingcondensers C1 and C2, an attenuator 63, the differential amplificationcircuit 30, the positive-side level judgment circuit 31, thenegative-side level judgment circuit 32, the gate circuit U3, and thelike. The attenuator 63 is the same as the attenuator 62 in the thirdembodiment. Other constituent elements are described in the firstembodiment, so that the descriptions thereof are omitted here. Theconversion unit including the differential amplification circuit 30, thepositive-side level judgment circuit 31, the negative-side leveljudgment circuit 32, the gate circuit U3, and the like, which convertsan input signal attenuated by the attenuator 63 to an output signal, isembedded in an integrated circuit 53. On the other hand, the attenuator63 is entirely arranged outside the integrated circuit 53.

In the receiving circuit according to the fourth embodiment, thecomparators U1 and U2 are comparators with hysteresis. Thus, each of thethreshold voltage on the positive side and the threshold voltage on thenegative side is provided with a hysteresis characteristic. Therefore,even when an AMI signal is affected by noise and reflected waves duringtransmission and consequently the receive waveform of the input signalis disturbed (see the upper portion of FIG. 4), the occurrence of theproblem that a pulse is divided into a plurality of pulses in the outputsignal due to the effects of noise and reflected waves is reduced (seethe output signal on the lower portion of FIG. 4).

In addition, the receiving circuit according to the fourth embodimenthas a configuration in which all of the resistors constituting theattenuator 63 are arranged outside the integrated circuit 53, and thusit is possible to maintain the attenuation rate substantially constanteven when the ambient temperature varies. Thus, the threshold levels(V1off, V1on, V2off, and V2on in FIG. 3) are stably maintained.

Therefore, in the receiving circuit according to the fourth embodiment,the frequency of occurrence of communication error is extremely reduced,compared with the conventional receiving circuit as shown in FIG. 9.

Note that in the receiving circuit according to the fourth embodiment,the supply voltage VCC5 is divided by resistors and the voltage sourceof the attenuator 63 is generated outside the integrated circuit 53.However, the receiving circuit may have a configuration in which thisvoltage source is generated inside the integrated circuit 53.

1. A receiving circuit that receives input of an AMI-coded signal,converts the signal to a binary output signal, and outputs the same, thereceiving circuit comprising: a first judging section configured tojudge whether an input signal is greater or less than a first thresholdon the positive side; a second judging section configured to judgewhether an input signal is greater or less than a second threshold onthe negative side; an output signal generating section configured togenerate the output signal based on judgment results of the firstjudging section and the second judging section; a first hysteresisgenerating section configured to provide a hysteresis characteristic tothe first threshold; and a second hysteresis generating sectionconfigured to provide a hysteresis characteristic to the secondthreshold.
 2. The receiving circuit according to claim 1, wherein thefirst hysteresis generating section sets the first threshold to a firstthreshold for increase on the positive side and a first threshold fordecrease on the positive side by providing a hysteresis characteristic,the first judging section inverts the result of judgment between twolevels when the voltage of the input signal exceeds the first thresholdfor increase on the positive side during the increase of the voltage ofthe input signal, and inverts the result of judgment between the twolevels when the voltage of the input signal lowers the first thresholdfor decrease on the positive side during the decrease of the voltage ofthe input signal, the second hysteresis generating section sets thesecond threshold to a second threshold for increase on the negative sideand a second threshold for decrease on the negative side by providing ahysteresis characteristic, and the second judging section inverts theresult of judgment between the two levels when the voltage of the inputsignal exceeds the second threshold for increase on the negative sideduring the increase of the voltage of the input signal, and inverts theresult of judgment between the two levels when the voltage of the inputsignal lowers the second threshold for decrease on the negative sideduring the decrease of the voltage of the input signal.
 3. A receivingcircuit that receives input of an AMI-coded differential signal,converts the signal to a binary output signal, and outputs the same, thereceiving circuit comprising: a differential amplifying sectionconfigured to convert the differential signal to a normal signal; afirst judging section and a second judging section configured to judgewhether the normal signal is greater or less than a threshold; an outputsignal generating section configured to generate the output signal basedon judgment results of the first judging section and the second judgingsection; a first hysteresis generating section configured to provide ahysteresis characteristic to a threshold of the first judging section;and a second hysteresis generating section configured to provide ahysteresis characteristic to a threshold of the second judging section.4. A receiving circuit that receives input of an AMI-coded signal,converts the signal to a binary output signal, and outputs the same, thereceiving circuit comprising: an attenuator including a plurality ofelectronic components that is configured to attenuate an input signal;and a conversion unit configured to convert the input signal attenuatedby the attenuator to the output signal, the conversion unit beingembedded in an integrated circuit, and the electronic components of theattenuator being arranged outside the integrated circuit.
 5. Thereceiving circuit according to claim 4, wherein the conversion unit hasa differential amplifying section configured to convert the input signalfrom a differential signal to a normal signal, and an output signalgenerating portion configured to convert the normal signal to the outputsignal.
 6. The receiving circuit according to claim 4, wherein a powersupply connected to the electronic components of the attenuator flowsfrom inside to outside the integrated circuit.
 7. The receiving circuitaccording to claim 4, wherein a power supply connected to the electroniccomponents of the attenuator is generated inside or outside theintegrated circuit.
 8. The receiving circuit according to claim 5,wherein a power supply connected to the electronic components of theattenuator flows from inside to outside the integrated circuit.
 9. Thereceiving circuit according to claim 5, wherein a power supply connectedto the electronic components of the attenuator is generated inside oroutside the integrated circuit.